I. Field of the Disclosure
The technology of the disclosure relates generally to Fin Field Effect Transistors (FETs) (FinFETs), and particularly to use of diffusion breaks between adjacent elements in FinFET complementary metal oxide semiconductor (CMOS) circuits to improve performance.
II. Background
Transistors are essential components in modern electronic devices. Large numbers of transistors are employed in integrated circuits (ICs) in many modern electronic devices. For example, components such as central processing units (CPUs) and memory systems each employ a large quantity of transistors for logic circuits and memory devices.
As electronic devices become more complex in functionality, so does the need to include a greater number of transistors in such devices. However, as electronic devices are required to be provided in increasingly smaller packages, such as in mobile devices, for example, a greater number of transistors need to be provided in a smaller IC chip. This increase in the number of transistors is achieved in part through continued efforts to miniaturize transistors in ICs (i.e., placing increasingly more transistors into the same amount of space). In particular, node sizes in ICs are being scaled down by a reduction in minimum metal line width in the ICs (e.g., 65 nanometers (nm), 45 nm, 28 nm, 20 nm, etc.). As a result, the gate lengths of planar transistors are also scalably reduced, thereby reducing the channel length of the transistors and interconnects. Reduced channel length in planar transistors has the benefit of increasing drive strength (i.e., increased drain current) and providing smaller parasitic capacitances resulting in reduced circuit delay. However, as channel length in planar transistors is reduced such that the channel length approaches a magnitude similar to the depletion layer widths, short channel effects (SCEs) can occur that degrade performance more specifically, SCEs in planar transistors cause increased current leakage, reduced threshold voltage, and/or threshold voltage roll-off (i.e., reduced threshold voltage at shorter gate lengths).
In this regard, to address the need to scale down channel lengths in transistors while avoiding or mitigating SCEs, transistor designs alternative to planar transistors have been developed. One such alternative transistor design includes a Fin Field Effect Transistor (FET) (FinFET) that provides a conducting channel via a “Fin” formed from a substrate. Material is wrapped around the Fin to form the gate of the device. For example, FIG. 1 illustrates a conventional FinFET 100. The FinFET 100 includes a semiconductor substrate 102 and a Fin 104 formed from the semiconductor substrate 102. An oxide layer 106 is included on either side of the Fin 104. The FinFET 100 includes a source 108 and a drain 110 interconnected by the Fin 104 such that an interior portion of the Fin 104 serves as a conduction channel 112 between the source 108 and drain 110. The Fin 104 is surrounded by a “wrap-around” gate 114. The wrap-around structure of the gate 114 provides better electrostatic control over the channel 112, and thus helps reduce the leakage current and overcome other SCEs.
Although a FinFET, such as the FinFET 100, reduces leakage current and avoids or mitigates SCEs compared to planar transistors, ICs employing FinFETs continue to need increased performance. For example, an IC can include one or more complementary metal oxide semiconductor (CMOS) circuits that employ P-type and N-type FinFETs. Conventional fabrication processes can result in P-type and N-type FinFETs having varying performance characteristics, such that either the P-type FinFET or the N-type FinFET limits the performance of a corresponding CMOS circuit, which limits the performance of the IC. In this manner, it would be advantageous to fabricate P-type and N-type FinFETs so as to reduce or avoid performance limitations attributable to conventional fabrication processes.